1. Field of the Invention
The present invention relates to a method for extracting a clock, and more particularly, to a method for extracting a clock in a clock data recovery (CDR) system.
2. Description of the Related Art
Serial link is one of the important techniques to provide high transmission rate in high speed I/O. When data is transmitted with serial link, the clock data is not accompanied. In order to obtain accurate clock data, a clock data recovery system is commonly used to extract accurate clock data from the transmission data.
Among various methods for implementing the clock data recovery system, one is by using a Phase Locked Loop (PLL) circuitry to generate a clock signal, so as to perform phase tracking. The alternative method is by using an over-sampling technique to select an accurate data group.
FIG. 1 schematically shows a relationship between clock and data. Referring to FIG. 1, a point 11 in the diagram indicates a change in the data status. If the data is accessed on the point 11 (i.e. the data is accessed on the falling edge of the clock), data reading error is likely to occur. Accordingly, in order to extract an accurate clock data, the clock should be extracted in a position with no change in the data status.
FIG. 2A schematically shows a conventional method for extracting clock data. Please refer to FIG. 2A, it is assumed that 3×sampling is performed in FIG. 2A, or the sampling is performed for three times on one bit data. Therefore, three pulse signals S0, S1, and S2 appear during the sampling period, and the sampling period is divided into three periods G0, G1, and G2 by three pulse signals S0, S1, and S2. The area M1 surrounded by dotted line in FIG. 2A represents a period with data status change. It is known from FIG. 2A that since the maximum value of the area M1 (corresponding to the point 11 in FIG. 1) is within the period G1, when the pulse signals S1 and S2 are being generated, data status would have a lot of changes. Therefore, it is determined that the accurate clock data cannot be extracted when the pulse signals S1 and S2 are being generated. In other words, the clock data is extracted only when the pulse signal S0 is being generated.
However, since the data transmission patterns are irregular, and the amount of the sampling points is insufficient, the inaccurate extraction of the clock data is inevitably increased.
FIG. 2B schematically shows a case of extracting clock data in a conventional technique. Referring to FIG. 2B, it is apparent that the maximum value of the dotted-line area M2 is within the period G0. Therefore, based on the description above, the clock data is extracted when the pulse signal S2 is being generated. However, it is also observed that some data status change may still occur when the pulse signals S1 and S2 are being generated, and no data status change is observed when the pulse signal S0 is being generated. Accordingly, the clock data extracted on the pulse signal S2 is inaccurate, and the accurate clock data should be extracted only when the pulse signal S0 is being generated.
In order to resolve the problem mentioned above, other technique of extracting clock data had been developed. FIG. 3 schematically shows another conventional method for extracting clock data. Referring to FIG. 3, in such a conventional technique, when to extract the clock data is determined based on the accumulated information. Specifically, since the dotted-line area M3 may be drifted horizontally along with the jitter caused by the DC (low frequency) signal. Therefore, this conventional technique determines how many pulse signals occur in the dotted-line area M3 within a predetermined period of time Ts. When the number of the pulse signals occurring in the dotted-line area M3 exceeds a predetermined value during the predetermined period of time Ts, a pulse signal next to the originally selected one is selected. For example, as shown in FIG. 3, originally there is only one pulse signal S1 occurring in the dotted-line area M3, thus the clock data is extracted when the next pulse signal S2 is being generated. If the dotted-line area M3 had drifted horizontally to the dotted-line area M3′ and contains the pulse signal S2 due to the impact of the DC signal (in other words, there are two pulse signals (S1 and S2) in the dot-line area M3′), the originally selected pulse signal S2 is replaced by the pulse signal S0 for extracting the clock data, thus the extraction error shown in FIG. 2B is overcome.
In the conventional technique of extracting clock data mentioned above, the tolerance of jitter margin caused by the DC signal is represented as follows:
                    2        ×                  (                                    Tui              3                        -            Ts            -            Tmismatch            -            Tphase                    )                                    (        1        )            where Tui represents a whole sampling period, Ts represents an area required for at least one change, Tui is divided by 3 to indicate that each bit is sampled three times; Tmismatch represents a time difference caused by the random jitter and the inconsistency of two different phases, and Tphase represents a time difference due to the noise. In addition, the reason for multiplying equation (1) by 2 is because the dotted-line area M3 drifts right or left, and the total tolerance of jitter margin for the whole system should be two times of it.
It is known from equation (1) that accumulating sufficient sampling points is required for accurately determining the time point of extracting the clock data, which inevitably increases the manufacturing cost and system complexity. Accordingly, when the number of the sampling points is getting bigger (i.e. the value of N is getting higher), the jitter margin of whole system is decreased, thus deteriorating the system accuracy and reliability.